1. Field of the Invention
The present invention relates to a semiconductor circuit, and in particular, relates to a shift register including a transistor. Moreover, the present invention relates to a display device including a semiconductor circuit and an electronic appliance including the display device.
Note that a semiconductor circuit mentioned in this specification indicates overall circuits which can work by utilizing semiconductor characteristics.
2. Description of the Related Art
In recent years, development of display devices such as a liquid crystal display device and a light emitting device have been actively carried out in accordance with increase in demand for portable apparatuses. In particular, a technique for forming a pixel circuit and driver circuits (hereinafter, referred to as internal circuits) including a shift register circuit and the like by using transistors formed using a polycrystalline semiconductor over an insulator, greatly contributes to miniaturization and reduction in power consumption, and therefore, this technique has been actively developed. The internal circuits formed over the insulator are connected to a controller IC and the like (hereinafter, referred to as external circuits) through an FPC and the like so that operation of the internal circuits are controlled.
As a shift register circuit constituting part of a conventional internal circuit, a shift register circuit including shift registers using clocked inverters is shown in each of FIG. 25 and FIG. 26. The shift register circuit shown in FIG. 25 includes n (n is an integer equal to or more than 3) stages of shift registers. Shift registers of 4 stages among the n stages of the shift registers are shown here. In FIG. 25, a single shift register includes a clock signal CK, an inverted clock signal CKb, a first clocked inverter CKINV1, a second clocked inverter CKINV2, an inverter INV, and an input signal SP. Further, in FIG. 25, a shift register in the i-th (i is a natural number equal to or less than n) stage is denoted by SRi.
In FIG. 26, only shift registers (SR1 and SR2) of 2 stages among the shift registers shown in FIG. 25 are denoted by transistors. In the shift register SR1 in the first stage, a first clocked inverter CKINV1 includes p-channel transistors 2501a and 2501b, and n-channel transistors 2501c and 2501d. A second clocked inverter CKINV2 includes p-channel transistors 2502a and 2502b, and n-channel transistors 2502c and 2502d. An inverter INV includes a p-channel transistor 2503a and an n-channel transistor 2503b. A specific description about the shift register SR2 in the second stage is omitted in this specification. As shown in FIG. 26, in the shift register SR2, signals (CK, CKb, and the like) to be input are inverted.
FIG. 27 shows a timing chart explaining a method for driving the shift registers having the structures shown in FIG. 25 and FIG. 26.
To provide a simple explanation, power supply voltage of a shift register (an internal circuit) is set to be 10 V (high potential power source Vdd is set to be 10 V and low potential power source Vss is set to be 0 V), and amplitude voltage of a pulse signal such as a click signal CK, an inverted clock signal CKb, or an input signal, which are input from an external circuit, is set to be 3 V (a high potential level (which is also referred to as an H level, H potential, or H), and a low potential level (which is also referred to as an L level, L potential, or L) is set to be 0 V). An IC constituting part of an external circuit is operated at lower power supply potential than the internal circuit.
The first clocked inverter CKINV1 will be specifically described. In the p-channel transistor 2501a, a case where a source of the p-channel transistor 2501a is input with 10 V of the high potential power source Vdd and a gate of the p-channel transistor 2501a is input with 3 V, which is H potential of a clock pulse CK or an inverted clock pulse CKB, i.e., a case where the H potential is input to the gate of the p-channel transistor to turn the p-channel transistor off, will be described. In this case, a potential difference between the gate and the source of the p-channel transistor 2501a is 7 V. If an absolute value of threshold voltage of the p-channel transistor 2501a is lower than 7 V, the p-channel transistor 2501a is remained turned on so that a conduction state is made between the source and the drain. Therefore, since the p-channel transistor, which is normally required to be remained turned off, is remained turned on, output in the shift register is not normally performed (see a dashed line 2701 in FIG. 27), and hence, there is a high probability of causing malfunction (see patent document 1).
Further, in order to prevent the malfunction due to the above reason, in a conventional shift register, after amplitude voltage of a pulse signal such as a clock pulse CK or a start pulse SP is increased to be almost equal to power supply voltage of the shift register through a level shifter, the pulse signal is input. For example, in order to operate an internal circuit accurately by using a signal with amplitude of about 3 V of an external circuit, there is a shift register circuit having a structure in which a level shift portion is disposed in each stage (e.g., see patent document 2).
[Patent Document 1]: Japanese Patent Application Laid-Open No. 2003-141893
[Patent Document 2]: Japanese Patent Application Laid-Open No. 2000-339985
There is a case where a threshold value of a transistor is varied due to variations in length and width of a gate and variations in thickness of a gate insulating film or the like, which are caused due to differences in manufacturing processes and substrates to be used, so that the threshold value is different from an expected value. In this case, when a signal with small amplitude is used in a digital circuit using two logic levels of “1” and “0”, the digital circuit is sometimes not operated accurately due to an adverse influence of variations in threshold value.
In an active matrix display device, the number of transistors is increased in the above described shift register circuit with increase in rows and columns of a pixel portion. Therefore, there is a problem that the yield attributable to variations in transistors with increase in the number of transistors is degraded.